Transistor channel lengths have become smaller to increase circuit density and to improve switching performance in integrated circuits. Power supply voltages have also been reduced to improve switching performance of transistors in integrated circuits. To accommodate the lower power supply voltages, transistors have been designed with lower threshold voltages for the gate-to-source voltage for which transistors turn-on. These transistors utilize a reduced logic swing between voltages that represent a logical one and a logical zero. That is, the difference between a minimum voltage representing a logical one and the maximum voltage representing a logical zero is reduced.
For example, the maximum voltage representing a logical zero may be 500 millivolts (mv) and the minimum voltage representing a logical one may be 2.4 volts (v) at the input/output interface to a packaged integrated circuit for a power supply of 3.3 volts. To speed logic switching internally, the maximum voltage representing a logical zero may be 100 millivolts and the minimum voltage representing a logical one may be 800 millivolts for a power supply of 1.25 volts, for example. With a reduced power supply, circuitry need only logically swing 700 millivolts in contrast to logically swinging one-thousand nine-hundred millivolts (e.g., 1.9 volts). Thus, lowering the power supply may increase performance if a transistor is compensated with smaller channel lengths and appropriate turn-on threshold voltages.
However, many other circuits (including other integrated circuits) that interface externally to an integrated circuit still require a larger logic swing, such as a maximum logical zero voltage of 500 millivolts and the minimum logical one voltage of 2.4 volts for a power supply of 3.3 volts. In which case, level translators are used to translate one set of logic levels to another.
One level translator may be formed out of a differential comparator having a differential input. A data input with one logic level is coupled to a first input of the comparator and an inverted data input is coupled to a second input of the comparator. As the comparator is provided with a power supply associated with a second set of logic levels with a swing greater than the first, the comparator can translate the logic levels at its inputs into the second logic levels at its output. The comparator may be a complementary metal oxide semiconductor comparator and use n-channel field effect transistors (NFETs) in a differential pair configuration to provide the differential input to the comparator. The comparator may further include a pair of cross-coupled p-channel field effect transistors (PFETs) to pull-up the output of the comparator to the logical one level of the second set of logic levels. The comparator may further include a cascode NFET and a cascode PFET in series together in each differential leg between the NFET of the differential pair and the PFET of the cross-coupled pull-up. However the cascode NFET and the cascode PFET can slow down the level translation and delay the output response. This is not acceptable in high speed integrated circuits.